1. Technical Field
This disclosure relates to processors, and more specifically to branch prediction within processors.
2. Description of the Related Art
Instruction set architectures (ISAs) typically include call and return instructions to facilitate the performance of procedural calls (i.e., function calls or subroutine calls). To make a procedural call, an instruction sequence may include a call instruction that is executable to cause the processor to begin executing the procedure. In particular, the call instruction may be executable to change a program counter of the processor to the location of the instructions in the procedure. The processor may then begin fetching and executing instructions at that location. Once the procedure completes, a return instruction may be executed to return from the procedure call by replacing the program counter with the location of the calling program sequence. This location, referred to as a return address, may be the address of the instruction that follows the call instruction.
To keep track of the return address, a processor may store a return address in a register or push the return address onto a call stack in main memory when the processor initially executes the call instruction. The processor may then retrieve the return address and load the return address into the program counter when the return instruction is subsequently executed. A problem with storing return addresses in this manner is that retrieving them can be time consuming and reduces instruction throughput as fetching may be delayed for the retrieval of return addresses.